A true two phase CCD refers to a device in which there are two physical gates per pixel, with each gate having both a transfer and a storage region formed in the silicon under it. There are two voltage phase lines .PHI..sub.1 and .PHI..sub.2. The charge coupling concept is used in frame transfer and interline transfer CCD image sensing devices. An example of a frame transfer area image sensor 10 is shown in FIG. 1.
A schematic cross-section for a true two phase CCD is shown in FIG. 1a. A true two phase CCD is described in detail in commonly assigned U.S. Pat. No. 4,613,402 to Losee and Lavine. A true two phase CCD has storage and transfer regions beneath each phase gate. In FIG. 1a the phase gates are labeled by either first or second polycrystalline silicon (poly-Si), and the transfer and storage regions by regions (1) and (2) for .PHI..sub.1 and (3) and (4) for .PHI..sub.2. In this disclosure only n-buried channel devices will be considered. This invention applies equally to p-buried channel devices. For an n-channel CCD, which is illustrated, the buried channel is formed by an n-type doping in a p-type substrate or in a p-well in an n-type substrate. The transfer and storage buried channel regions are differentiated by less or more of the n-buried channel doping, respectively. U.S. Pat. No. 4,613,402 discloses a detailed procedure for making true two phase CCD devices.
The electrostatic potential band diagram through one of the phase gate electrodes, the buried channel and the substrate of an image pixel is shown in FIG. 2. The buried channel is shown reverse biased and with a positive gate voltage, Vg, to create a depleted surface. In this situation, the Fermi level (E.sub.F), although not shown, will be near the middle of the band gap at the oxide-Si interface. In a buried channel CCD, dark current arises from three main sources: (1) generation from a mid-gap state resulting from either the disrupted lattice or an impurity at a depleted Si-SiO.sub.2 interface, (2) generation in the depletion region as a result of an impurity or defect with a mid-gap state and (3) diffusion of electrons to the buried channel from the substrate. All three sources, result in spurious charges being collected as signal in the buried channel. The mechanism for dark current generation both at the surface and in the depletion region is illustrated in FIG. 2 and is as follows: A generation site (defect) emits an electron (negative charge) into the conduction band in the buried channel and a hole (positive charge) into the valence band. In both cases, the electron is captured by the buried channel as dark signal, and if the spatial region where the hole is emitted to the valence band is depleted of majority carriers then the holes will migrate away from their point of generation thus leaving the region depleted of majority carriers. A hole generated in the depletion region is driven to the substrate. A hole generated at the surface goes laterally to a channel stop region, again leaving the surface depleted of majority carriers. Since the state of the generation regions is now exactly the same as before the electron and hole emission events, the surface and depletion region defects continue to generate electron and hole pairs, thus acting as sources of dark current. This generation process ceases only if an excess of either electrons or holes develop in the region where the defect exists. Modern fabrication technology has reduced the concentrations of both defects in the depletion region and also defects leading to bulk current to such an extent that the surface state generation mechanism is the dominant source of dark current in buried channel CCDs.
Accordingly, it is an object of this invention to reduce this surface state component of dark current.